1. Field of the Invention
The present invention relates to a clock generation circuit in a communication network and, more specifically, to the systems and methods for generating a digitally compensated highly stable holdover clock.
2. Discussion of Related Art
Many communication networks and devices operate using a reference clock backed by a holdover clock. Network clocks are generally traceable to the reference clock. If the reference clock is unavailable, the network clocks should be traceable to the holdover clock. Certain communication networks require highly stable reference and holdover clocks. For example, the current 2G and the future 3G wireless networks have specific stability requirements for the reference clock, ranging from 0.01 ppm to 0.1 ppb. When the reference clock is lost, the stability of the holdover clock becomes crucial to ensuring reliable connections in the network.
Currently, a holdover clock is generally implemented using either a rubidium crystal oscillator (“RbXO”) or an oven controlled crystal oscillator (“OCXO”) with control voltage inputs. A RbXO can generally meet the strict stability requirements easily, but is very expensive. In comparison, OCXOs are inferior to a RbXO in terms of stability, but are much less expensive. With carefully designed peripheral circuits, it is possible for OCXOs to meet the stability requirements, but at the cost of increased system complexity.
All solutions of holdover clocks based on OCXOs suffer from aging effects of the crystals, which causes the output frequency to drift. As a result, calibration and compensation has to be performed regularly, normally by changing the control voltage of the OCXO. This approach requires the use of a voltage controlled OcxO (“VC-OCXO”).
In a typical clock generation circuit, a phase-locked loop with a VC-OCXO is used to generate a holdover clock based on an input reference clock. A phase and frequency detector generates an error signal representing the phase difference between an input reference clock signal and a feedback signal. The error signal is filtered in a filter, and the filtered error signal is then converted to an analog signal, which represents a voltage signal used to control the output signals of the VC-OCXO. The VC-OCXO outputs signals with different frequencies according to the voltage signal. A feedback divider divides the frequency of the VC-OCXO output signal to generate the feedback signal for the phase and frequency detector. One major disadvantage of this approach is that the voltage signal used to control the output clock signal of a VC-OCXO is prone to circuit noise; therefore, accuracy or stability of the output clock signal is often degraded. Furthermore, such clock generation systems are known to be realized only by discrete circuits.
Therefore, it is desirable to develop a solution capable of generating a highly stable holdover clock with both improved accuracy and great cost reduction but without increased system complexity.